Inter-spikes-intervals exponential and gamma distributions study of neuron firing rate for SVITE motor control model on FPGA

This paper presents a statistical study on a neuro-inspired spike-based implementation of the Vector-Integration-To-End-Point motor controller (SVITE) and compares its deterministic neuron-model stream of spikes with a proposed modification that converts the model, and thus the controller, in a Poisson like spike stream distribution. A set of hardware pseudo-random numbers generators, based on a Linear Feedback Shift Register (LFSR), have been introduced in the neuron-model so that they reach a closer biological neuron behavior. To validate the new neuron-model behavior a comparison between the Inter-Spikes-Interval empirical data and the Exponential and Gamma distributions has been carried out using the Kolmogorov–Smirnoff test. An in-hardware validation of the controller has been performed in a Spartan6 FPGA to drive directly with spikes DC motors from robotics to study the behavior and viability of the modified controller with random components. The results show that the original deterministic spikes distribution of the controller blocks can be swapped with Poisson distributions using 30-bit LFSRs. The comparative between the usable controlling signals such as the trajectory and the speed profile using a deterministic and the new controller show a standard deviation of 11.53 spikes/s and 3.86 spikes/s respectively. These rates do not affect our system because, within Pulse Frequency Modulation, in order to drive the motors, time length can be fixed to spread the spikes. Tuning this value, the slow rates could be filtered by the motor. Therefore, this SVITE neuro-inspired controller can be integrated within complex neuromorphic architectures with Poisson-like neurons

Live Demonstration: Real-time neuro-inspired sound source localization and tracking architecture applied to a robotic platform

This live demonstration presents a sound source localization and tracking system implemented with Spike Signal Processing (SSP) building blocks on FPGA devices. The system architecture is based on the ability of the mammalian auditory system to locate the direction of a sound in the horizontal plane using the interaural intensity difference. We used a binaural Neuromorphic Auditory Sensor to obtain spike rates similar to those generated by the inner hair cells of the human auditory system and the component that obtains the interaural intensity difference is inspired by the lateral superior olive. The spike stream that represents the interaural intensity difference is used to turn a robotic platform towards the sound source direction. The system was tested with pure tones (1-kHz, 2.5-kHz and 5- kHz sounds) with an average error of 2.32 degrees.Ministerio de Economía y Competitividad TEC2016-77785-

Application of bus emulation techniques to the design of a PCI/MC68000 bridge

Bridges easy the interconnection and communication of devices that operate using different buses. In fact, we can see a computer as a hierarchy of buses to which devices are connected. In this paper we design a PCI/MC68000 bridge in order to improve communications between a Personal Computer and a MC68000 based system. The previous interface between both devices was based on the old 16-bit ISA bus, which represented a bottleneck in their communication. However, the methodology described here is generic and can be applied to the design of PCI bridges to other buses. We finish this work with an analysis of the bridge performance improvement which can also be easily adapted to other situations. As an example our interface is used in an interesting situation, i.e., updating the obsolete control unit of a highly valuable system (an industrial robot)

Influence of Input/output Operations on Processor Performance

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission

SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller

This paper presents an implementation of a neuro-inspired algorithm called VITE (Vector Integration To End Point) in FPGA in the spikes domain. VITE aims to generate a non-planned trajectory for reaching tasks in robots. The algorithm has been adapted to work completely in the spike domain under Simulink simulations. The FPGA implementation consists in 4 VITE in parallel for controlling a 4-degree-of-freedom stereo-vision robot. This work represents the main layer of a complex spike-based architecture for robot neuro-inspired reaching tasks in FPGAs. It has been implemented in two Xilinx FPGA families: Virtex-5 and Spartan-6. Resources consumption comparative between both devices is presented. Results obtained for Spartan device could allow controlling complex robotic structures with up to 96 degrees of freedom per FPGA, providing, in parallel, high speed connectivity with other neuromorphic systems sending movement references. An exponential and gamma distribution test over the inter spike interval has been performed to proof the approach to the neural code proposed.Ministerio de Economía y Competitividad TEC2012-37868-C04-0

A game-based approach to the teaching of object-oriented programming languages

Students often have difficulties when trying to understand the concepts of object-oriented programming (OOP). This paper presents a contribution to the teaching of OOP languages through a game-oriented approach based on the interaction with tangible user interfaces (TUIs). The use of a specific type of commercial distributed TUI (Sifteo cubes), in which several small physical devices have sensing, wireless communication and user-directed output capabilities, is applied to the teaching of the C# programming language, since the operation of these devices can be controlled by user programs written in C#. For our experiment, we selected a sample of students with a sufficient knowledge about procedural programming, which was divided into two groups: The first one had a standard introductory C# course, whereas the second one had an experimental C# course that included, in addition to the contents of the previous one, two demonstration programs that illustrated some OOP basic concepts using the TUI features. Finally, both groups completed two tests: a multiple-choice exam for evaluating the acquisition of basic OOP concepts and a C# programming exercise. The analysis of the results from the tests indicates that the group of students that attended the course including the TUI demos showed a higher interest level (i.e. they felt more motivated) during the course exposition than the one that attended the standard introductory C# course. Furthermore, the students from the experimental group achieved an overall better mark. Therefore, we can conclude that the technological contribution of Sifteo cubes – used as a distributed TUI by which OOP basic concepts are represented in a tangible and a visible way – to the teaching of the C# language has a positive influence on the learning of this language and such basic concepts

An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata

Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event- Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata (CA) is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution. This paper presents a software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation. Furthermore this simulator produces VHDL for testing the AER-CA into the FPGA of the USBAER AER-tool.Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

Frequency Analysis of a 64x64 Pixel Retinomorphic System with AER Output to Estimate the Limits to Apply onto Specific Mechanical Environment

The rods and cones of a human retina are constantly sensing and transmitting the light in the form of spikes to the cortex of the brain in order to reproduce an image in the brain. Delbruck’s lab has designed and manufactured several generations of spike based image sensors that mimic the human retina. In this paper we present an exhaustive timing analysis of the Address-Event- Representation (AER) output of a 64x64 pixels silicon retinomorphic system. Two different scenarios are presented in order to achieve the maximum frequency of light changes for a pixel sensor and the maximum frequency of requested directions on the output AER. Results obtained are 100 Hz and 1.66 MHz in each case respectively. We have tested the upper spin limit and found it to be approximately 6000rpm (revolutions per minute) and in some cases with high light contrast lost events do not exist.Ministerio de Ciencia e Innovación TEC2009-10639- C04-0

A FPGA Spike-Based Robot Controlled with Neuro-inspired VITE

This paper presents a spike-based control system applied to a fixed robotic platform. Our aim is to take a step forward to a future complete spikes processing architecture, from vision to direct motor actuation. This paper covers the processing and actuation layer over an anthropomorphic robot. In this way, the processing layer uses the neuro-inspired VITE algorithm, for reaching a target, based on PFM taking advantage of spike system information: its frequency. Thus, all the blocks of the system are based on spikes. Each layer is implemented within a FPGA board and spikes communication is codified under the AER protocol. The results show an accurate behavior of the robotic platform with 6-bit resolution for a 130º range per joint, and an automatic speed control of the algorithm. Up to 96 motor controllers could be integrated in the same FPGA, allowing the positioning and object grasping by more complex anthropomorphic robots.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Economía y Competitividad TEC2012-37868-C04-0

Low-Cost Throttle-By-Wire-System Architecture For Two-Wheeler Vehicles

This paper investigates the performance of a low-cost Throttle-by-Wire-System (TbWS) for two-wheeler applications. Its consisting of an AMR throttle position sensor and a position controlled stepper motor driven throttle valve actuator. The decentralized throttle position sensor is operating contactless and acquires redundant data. Throttle valve actuation is realized through a position controlled stepper motor, sensing its position feedback by Hall effect. Using a PI-controller the stepper motors position is precisely set. Sensor and actuator units are transceiving data by a CAN bus. Furthermore, failsafe functions, plausibility checks, calibration algorithms and energy saving modes have been implemented. Both modules have been evaluated within a Hardware-in-the-Loop test environment in terms of reliability and measurement/positioning performance before the TbWS was integrated in a Peugeot Kisbee 50 4T (Euro 5/injected). Finally, the sensor unit comes with a measurement deviation of less then 0.16% whereas the actuator unit can approach throttle valve positions with a deviation of less then 0.37%. The actuators settling time does not exceed 0.13s while stable, step-loss free and noiseless operation